January JEDEC. STANDARD. DDR2 SDRAM SPECIFICATION be addressed to JEDEC Solid State Technology Association, Wilson Boulevard. DDR2 SDRAM is a double data rate synchronous dynamic random-access memory interface. It superseded the original DDR SDRAM specification, and is superseded by .. JEDEC standard: DDR2 SDRAM Specification: JESDF, November ** ยท JEDEC. The JEDEC memory standards are the specifications for semiconductor memory circuits and Memory modules of the DDR2-SDRAM type are available for laptop, desktop, and server computers in a wide selection of capacities and access.

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The purpose of the standard is specifciation promote the uniform use of symbols, abbreviations, terms, and definitions throughout the semiconductor industry. An alternative system is found in Amendment 2 to IEC By using this site, you agree to the Terms of Use and Privacy Policy.

DDR2’s bus frequency is boosted by electrical interface improvements, on-die terminationprefetch buffers and off-chip drivers. These chips are mostly standard DDR chips that have been tested and rated to be capable of operation at higher clock rates by the manufacturer.


This page was last edited on 2 Augustat JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally.

This article needs to be updated. Power savings are achieved primarily due to an improved manufacturing process through die shrinkage, resulting in a drop in operating voltage 1. From Wikipedia, the free encyclopedia.


Retrieved August 25, The definitions of kilo, giga, and mega based on powers of two are included only to reflect common usage. During an access, four bits were read or written to or from a four-bit-deep prefetch queue. Retrieved from ” https: From Wikipedia, the free encyclopedia.


Dynamic random-access memory DRAM. Ddrr2 least one manufacturer dxr2 reported this reflects successful testing at a higher-than-standard data rate [4] whilst others simply round up for the name. The specification contains definitions of the commonly used prefixes kilomegaand giga usually combined with the units byte and bit to designate multiples of the units.

These cards actually use standard DDR2 chips designed for use as main system memory although operating with higher latencies to achieve higher clockrates.

It had severe overheating issues due to the nominal DDR voltages. This packaging change was necessary to maintain signal integrity at higher bus speeds. This page was last edited on 11 Januaryat In addition to double pumping the data bus as in DDR SDRAM transferring data on the rising and falling edges of the bus clock signalDDR2 allows higher bus speed and requires lower power by running the internal clock at half the speed of the data bus.

Both performed worse than the original DDR specification due to higher latency, which made total access times longer. Retrieved from ” https: This committee consists of members from manufacturers of microprocessors, memory ICs, memory modules, and other components, as well as component integrators, such as video card and personal computer makers.

Views Read Edit View history. Such chips draw significantly more power than slower-clocked chips, but usually offered little or no improvement in real-world performance.

DIMMs are identified by their peak transfer capacity often called bandwidth. Alternatively, DDR2 memory operating at twice the external data bus clock rate as DDR may provide twice the bandwidth with the same latency.

This is because DDR2 memory modules dd2 data on a bus that is 64 data bits wide, and since a byte comprises 8 bits, this equates to 8 bytes of data per transfer. Please update this article to reflect recent events or newly available information. The document notes that these prefixes are used in their decimal sense for serial communication data rates measured in bits.

Wikipedia articles in need of speciification from Cdr2 All Wikipedia articles in need of updating. Thus, DDR2 memory must be operated at twice the data rate to achieve the same latency.



The standards specify the physical and electrical characteristics of the modules, and include the data for computer simulations of the memory module operating in a system. By using this site, you agree to the Terms of Use and Privacy Policy. The two factors combine to produce a total of four data transfers per internal clock cycle. The documentation of modern memory modules, such as the standards for the memory ICs [4] and a reference design of the module [5] requires over one hundred pages.

DDR2 was introduced in the second quarter of at two initial clock rates: However, further confusion has been added to the mix with the appearance of budget and mid-range graphics cards which claim to use “GDDR2”.

The specification notes that these prefixes are included in the document only to reflect common usage. The lower memory clock frequency may also enable power reductions in applications that do not require the highest available data rates. Bandwidth is calculated by taking transfers per second and multiplying by eight.

These chips cannot achieve the clock rates of GDDR3 but are inexpensive and fast enough to be used as memory on mid-range cards. The standards specify memory module label formats for end-user markets.

Views Read Edit View history.

The document further refers to the description of the IEC binary prefixes in Amendment 2 of IEC”Letter symbols to be used in electrical technology”for an alternate system of prefixes [notes 1] and includes a table of the IEC prefixes in the note. The specification defines the two common units of information: This queue received or transmitted its data over the data bus in two data bus clock cycles each clock cycle transferred two bits of data.

In other projects Wikimedia Commons. However, latency is greatly increased as a trade-off.